A recent trend toward high integration of semiconductor devices uses a gate electrode of a memory device that occupies an increasingly smaller space. In this regard, the width and contact area of the gate electrode may be gradually reduced. Accordingly, contact resistance and sheet resistance of the gate electrode tend to increase, which may undesirably lower the operating speed. Therefore, a salicide (self-aligned silicide) process in which a metal gate is employed in order to reduce the resistance has been studied and developed.
However, since a highly integrated semiconductor device may have a reduced gate line width compared to a height of the gate electrode, it may not be easy to deposit the metal material during the salicide process. In addition, in a case where the metal gate and the salicide process are both employed, the metal gate may be dissolved in a wet-etching solution used in the salicide process or a metal stripping material. As such the metal gate may be damaged. Further, the more highly integrated the semiconductor device, the smaller the manufacturing margin thereof. Thus, in a case where misalignment occurs during the salicide process, a probability of the metal gate being damage may be increased.